ATE (Automatic Test Equipment) is an automated testing platform used in semiconductor manufacturing to evaluate chip performance and detect defects. It is the most important type of semiconductor inspection equipment, accounting for approximately 63% of the total value. The following provides a detailed introduction from three aspects: classification, tool composition, and testing flow.
Classification of ATE
ATE test equipment is used throughout the entire chip production cycle, including design verification, wafer manufacturing, and packaging test. It can be divided into the following categories:
Inspection during wafer manufacturing: This stage focuses on appearance inspection and belongs to physical and functional testing, aiming to find defects generated during wafer fabrication.
Inspection during packaging and testing:
Circuit Probing (CP): Before packaging, electrical performance testing is performed on the chips on the wafer to screen out qualified dies.
Final Test (FT): After packaging, final electrical performance testing is conducted on finished chips to ensure they meet quality standards.
Other types of testing:
Quality Assurance Test: Sampling is performed on chips that have passed testing for quality control.
Pre/Post Burn-In: Burn-in testing accelerates chips into a stable working state and screens out early failure products.
Military Testing: More stringent testing for military-grade chips with high reliability requirements.
Failure Analysis: The test results are used to improve process, optimize design, and enhance yield.
Tool Composition of ATE
Taking a CP test platform as an example, ATE mainly consists of the following three parts:
Wafer Prober: Also called a probe station, it is available in manual, semi-automatic, and fully automatic types. During testing, the x and y coordinates of each die are used to construct an electronic wafer map. The test results (pass/fail) are displayed on the map for subsequent packaging selection.
Wafer Tester: It mainly performs functional testing of the wafer. Under external control from a workstation, it generates the required voltage, current, and timing signals according to the test program, reads the response signals from the device under test, and determines whether the chip is qualified.
Probe Card: It is responsible for fixing the probes and making direct contact with the wafer. It consists of a control card and probes. The probes contact the pads or bumps on the die and lead out the chip signals, working with peripheral test instruments and software control to realize automated measurement. For different pad layouts and test requirements, Hansheng Automation can custom-machine probe card holders, alignment fixtures, and other precision interface components to ensure stable contact and accurate signal transmission.
Testing Flow of ATE
Taking the testing of a batch of wafers as an example, the ATE testing flow includes the following steps:
Step 1: Distinguish chips
Chips are usually designed with several test mode functions. By configuring the pins, the chip enters a specified test state to complete different types of testing:
ATPG: Outputs WGL or STIL format files for the tester.
BIST (Built-In Self Test) logic: Uses self-test logic to complete tests of ROM/RAM/Flash and other functions.
Function Test Mode: Adds hardware logic for special functions such as ADC/DAC/clock for testing.
Step 2: Select test house and tester model
According to chip type, test content, test specifications, and cost, choose a capable test house and a matching tester model.
Step 3: Fabricate the probe card and develop the test program
Probe card fabrication: Based on the die coordinates and pin pitch information determined in the chip design stage, the probes and peripheral circuits are made.
Test program development: The test program controls the entire test process. Engineers provide files in WGL/STIL/VCD format, convert them into the format required by the tester, and add other test programs.
Step 4: Debugging and result analysis
The test results generate a wafer map file and a log file (such as an STD file):
Wafer map: Contains yield, test time, the number of errors in each BIN, and die positions.
Log file: Records specific test results.
Engineers analyze the data to decide whether to enter mass production. During debugging, the test vectors are divided into different BINs according to the test plan to locate error positions, and the pattern and test program are modified until all BINs pass.
Step 5: Further debugging and process optimization
After entering the mass production stage, the test flow is adjusted based on large amounts of test statistics. It is decided whether to retest failed dies (a certain proportion of errors can be corrected). Yield stability is monitored. If the yield is continuously low, testing is stopped for data analysis or communication with the foundry. Finally, the CP test results are handed over to the packaging factory to complete the mass production transfer.
